It is well known to construct an asynchronous first-in first out FIFO buffer using counters, adders, and combinatorial logic to generate a so-called full flag for indicating when the FIFO is full. Another way to generate a full flag is by directly decoding the input counters with combinatorial logic. Both of these methods have long flag delays because the amount of circuitry between the input clocks and the output flag. To overcome the long flag delays associated with the combinatorial decode methods some form of look-ahead technique is employed. In the past this look-ahead technique has been done with a look-ahead decode path for generating a full-1 status flag, and latches and filters near the output to provide the actual full flag. This look-ahead technique provides reduced delay in generating the full flag, but has suffered in the past from metastability problems introduced because of the latches that are trying to sample the asynchronous full-1 flag based on some combination of the asynchronous read and write clocks.
In a typical counter/adder decode method there are two counters, one for each the read and write clocks. These two counters are reset to zero upon master reset and are incremented based only on their respective clocks. The outputs of the read and write counters are fed into a subtractor that calculates the difference between the number of locations written and the the number of locations read. This difference is then fed into combinatorial logic to determine if the FIFO is full. The combinatorial logic output is then used to drive the output flag.
Another method, called the direct decode method, uses the counters similar to the counters used in the counter/adder method. Instead of having a subtractor on the outputs, combinatorial logic is used to decode when the FIFO is full. This is done by taking the exclusive-OR (XOR) of the write and read counters. This combinatorial logic can be realized by generating a truth table for the full flag with respect to the write and read counters input variables. While the direct decode method reduces the amount of logic required to generate a full status flag and improves the speed of generating the full status flag as compared with the counter adder method, the direct decode method continues to have flag delays in the magnitude of 15-30 ns.